Flip chip bonding has been conventionally used as high density mount technology for mounting a semiconductor element on a printed circuit board or the like without packaging it. With this flip chip bonding technology, external terminals are formed on pads of a semiconductor element, and the pads of the semiconductor element and bonding pads on a printed circuit board are electrically and mechanically connected via the external terminals.
With flip chip bonding, however, the layout and size of external terminals are restricted by the layout and size of pads of a semiconductor element. The pad size of a semiconductor element is about 50 μm at a maximum and the pad space is about 100 μm. In a general printed circuit board using resin material as its base material, the size of a bonding pad is about 200 μm at a minimum and the bonding pad space is about 500 μm. Therefore, with mount technology using flip chip bonding, it is difficult to mount a semiconductor element on a printed circuit board made of resin material as its base material.
In order to solve the above-described problem associated with mount technology using flip chip bonding, there is a remarkable tendency that the size of a semiconductor device to be substantially equal to that of a semiconductor element. A package of such a semiconductor device is generally called a CSP (chip size package or chip scale package). Examples of CSP are described in JP-A-6-504408, Technical Report of the Institute of Electronics, Information and Communication Engineers “Development on Tape BGA type CSP”, CPM96-121, ICD96-160 (December, 1996) and the like.